The traditional way to recover a clock signal from a serial data bit stream is for the receiving system or circuit to generate a clock signal. The clock signal is synchronized to the incoming serial data bit stream, usually using a phase-locked loop or delay-locked loop. The receiving system's generated clock signals are synchronized with transitions in the incoming serial data bit stream.
Unlike the previously known methods, the present invention treats a subset of the transitions in the incoming Manchester or other bi-phase level encoded serial data bit stream as the clock signal itself, using a filter to filter out unwanted transitions in the received signal, retaining only the "informational" transitions in the received signal. The recovered clock is obtained by amplifying and reshaping the informational transitions. The circuit of the present invention does not use any analog or digital phase-locked loops or delay-locked loops. When using the same integrated circuit fabrication technology, circuitry using the present invention achieves similar speed performance as a typical phase-locked loop or delay-locked loop.
Advantages of the present invention are:
much higher jitter tolerance on the incoming signal than is practical using phase-locked loop technology. Jitter tolerance is vital for a clock and data recovery system. It is the most desirable characteristic of a clock and data recovery system. PA1 The present invention can be implemented using solely digital circuitry, which avoids the difficulties of mixing analog and digital circuits on a single semiconductor integrated circuit chip. PA1 Avoiding the use of phase-locked or delay-locked loops avoids the difficulties normally associated with providing a stable control system. PA1 The present invention uses much simpler circuitry than clock and data recovery circuitry utilizing phase-locked and delay-locked loop, which results in higher integration levels on a single semiconductor integrated circuit chip. A very large number of such clock and data recovery circuit blocks can be implemented on a single semiconductor integrated circuit chip. This is important because it enables integration of some types of systems on a single semiconductor integrated circuit chip which is not attainable using traditional clock and data recovery circuits. PA1 The present invention uses much less power than clock and data recovery circuitry utilizing phase-locked and delay-locked loop.